sync: update ggml
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a17ae7b7d2
commit
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2
ggml
2
ggml
@ -1 +1 @@
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Subproject commit b94c066ad4de62bda2a10a80131d4cd8112f7c65
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Subproject commit 9cc5cb27f97821482fbb99aea1e590e55bf89151
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@ -846,7 +846,7 @@ public:
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return NULL;
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return NULL;
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}
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}
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// it's performing a compute, check if backend isn't cpu
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// it's performing a compute, check if backend isn't cpu
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if (!ggml_backend_is_cpu(backend) && tensor->backend == GGML_BACKEND_CPU) {
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if (!ggml_backend_is_cpu(backend) && tensor->backend == GGML_BACKEND_TYPE_CPU) {
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// pass input tensors to gpu memory
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// pass input tensors to gpu memory
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auto backend_tensor = ggml_dup_tensor(compute_ctx, tensor);
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auto backend_tensor = ggml_dup_tensor(compute_ctx, tensor);
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@ -65,17 +65,20 @@ enum sd_type_t {
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SD_TYPE_Q8_0 = 8,
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SD_TYPE_Q8_0 = 8,
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SD_TYPE_Q8_1 = 9,
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SD_TYPE_Q8_1 = 9,
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// k-quantizations
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// k-quantizations
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SD_TYPE_Q2_K = 10,
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SD_TYPE_Q2_K = 10,
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SD_TYPE_Q3_K = 11,
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SD_TYPE_Q3_K = 11,
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SD_TYPE_Q4_K = 12,
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SD_TYPE_Q4_K = 12,
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SD_TYPE_Q5_K = 13,
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SD_TYPE_Q5_K = 13,
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SD_TYPE_Q6_K = 14,
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SD_TYPE_Q6_K = 14,
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SD_TYPE_Q8_K = 15,
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SD_TYPE_Q8_K = 15,
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SD_TYPE_IQ2_XXS = 16,
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SD_TYPE_IQ2_XXS = 16,
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SD_TYPE_IQ2_XS = 17,
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SD_TYPE_IQ2_XS = 17,
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SD_TYPE_IQ3_XXS = 18,
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SD_TYPE_IQ3_XXS = 18,
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SD_TYPE_IQ1_S = 19,
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SD_TYPE_IQ1_S = 19,
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SD_TYPE_IQ4_NL = 20,
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SD_TYPE_IQ4_NL = 20,
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SD_TYPE_IQ3_S = 21,
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SD_TYPE_IQ2_S = 22,
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SD_TYPE_IQ4_XS = 23,
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SD_TYPE_I8,
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SD_TYPE_I8,
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SD_TYPE_I16,
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SD_TYPE_I16,
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SD_TYPE_I32,
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SD_TYPE_I32,
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